Wednesday 25 January 2017 

Speaker: Kostas Manolopoulos (RAL/PPD)


Title: "An FPGA-based track finder for the CMS Phase-2 Level-1 Track Trigger Upgrade”

Abstract: The High Luminosity LHC is expected to be completed by 2026 and the CMS collaboration is preparing a major upgrade of its detector, referred to as Phase-2 Upgrade.  Amongst others, a new tracking system will be developed, where the upgraded tracker electronics will reconstruct trajectories of charged particles within a latency of a few microseconds, so that they can be used by the Level-1 trigger. For this purpose, an FPGA-based track finder has been implemented, utilising a fully time-multiplexed architecture, where track candidates are identified using a projective binning algorithm based on the Hough Transform. A hardware system based on the MP7 MicroTCA processing card has been assembled, demonstrating a realistic slice of the track finder in order to help gauge the performance and requirements for a full system. This talk will describe the system architecture and the algorithms employed, analyse the performance of the hardware demonstrator, highlight some of its results and discuss the prospects of a full scale track finder.